Integrated circuitry is typically fabricated on and within semiconductor substrates, such as bulk monocrystalline silicon wafers. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Electrical components fabricated on substrates, and particularly bulk semiconductor wafers, are isolated from adjacent devices by insulating materials, such as, silicon dioxide. One isolation technique uses shallow trench isolation, whereby trenches are cut into a substrate and are subsequently filled with an insulating material, such as, for example, silicon dioxide.
Integrated circuitry frequently comprises a densely-packed array of memory devices surrounded by so-called peripheral circuitry (i.e., circuitry which is peripheral to the memory array). Accordingly, a semiconductor substrate can be divided into a memory array region, and a region peripheral to the memory array region. Frequently, there will be an isolation trench formed between the memory array region and the peripheral region, with such trench being formed simultaneously with the shallow trench isolation regions.
A prior art method for forming various trenched isolation regions is described with reference to FIGS. 1-4. Referring initially to FIG. 1, a semiconductor construction 10 is illustrated at a preliminary processing stage. Construction 10 comprises a semiconductor substrate 12 which can correspond to, for example, a bulk monocrystalline silicon wafer. A patterned mask comprising layers 14 and 16 is formed over substrate 12. Layer 14 can comprise, consist essentially of, or consist of, for example, silicon dioxide; and layer 16 can comprise, consist essentially of, or consist of, for example, silicon nitride.
The patterned mask covers some regions of substrate 12, while leaving other regions exposed within gaps extending through the patterned mask. Trenches 18, 20 and 22 are formed to extend into substrate 12 within the gaps defined by the masking materials 14 and 16.
The substrate can be considered to comprise a defined memory array region 30 and a defined region 32 peripheral to the memory array region. The memory array region is a location of the substrate where memory devices will ultimately be formed in a tightly-packed array, and the peripheral region is a region of the substrate peripheral to the memory array. A dashed line 33 is provided to diagrammatically illustrate a boundary between the memory array region and the peripheral region.
Trenches 18 and 20 can correspond to so-called shallow trenches which are ultimately utilized for forming shallow trench isolation regions. The shallow trenches of shallow trench isolation regions can be any suitable depth, and frequently will be 3500 Å to 4000 Å deep. In the past, shallow trench isolation region trenches were typically kept to depths of less than 2000 Å, but it is now becoming common for the depths to be much deeper. The increasing depths of the trenches can improve isolation, but creates complications in filling the trenches.
The trench 22 is utilized for forming an isolation region between the memory array region and the peripheral region, and can be referred to as a moat between the memory array region and circuitry of the peripheral region. Such moat can be formed to a depth comparable to the depths of the shallow trench isolation regions, as shown, but is typically significantly wider than the shallow trench isolation regions. Accordingly, trench (or moat) 22 is shown to have a lower aspect ratio than the shallow trench isolation regions 18 and 20.
Although shallow trench isolation regions are shown being associated only with the memory array portion of the FIG. 1 construction, it is to be understood that shallow trench isolation regions can also be associated with peripheral circuitry, and typically it is desirable to form the shallow trench isolation regions associated with the peripheral circuitry simultaneously with the shallow trench isolation regions associated with the memory array circuitry, and also simultaneously with the formation of the isolation region trench 22 that separates peripheral region circuitry from the memory array region.
Referring next to FIG. 2, oxide 34 is provided within trenches 18, 20 and 22. The oxide can be formed by, for example, a high-density plasma deposition process utilizing SiH4 and O2 as precursors, and further utilizing argon as a carrier gas. Accordingly, the plasma of the high-density plasma process can be formed from a gas consisting essentially of SiH4, O2 and Ar. For purposes of interpreting this disclosure and the claims that follow, a high-density plasma is defined as a plasma having a density of greater than or equal to about 1010 ions/cm3.
High-density plasma processes are preferred for filling the trenches relative to other oxide-deposition processes, in that high-density plasma processes can avoid so-called bread-loafing. Bread-loafing occurs when deposited oxide pinches the top of a trench closed before the trench has been completely filled with oxide, and can thus result in formation of keyhole openings within the oxide. Such keyhole openings can degrade performance of oxide isolation regions. High-density plasma deposition processes advantageously form oxide more linearly along sidewalls of an opening than other oxide deposition processes, and so can more uniformly fill high-aspect-ratio openings than can other oxide deposition processes. However, some oxide material can still form along sidewalls of the openings during high-density plasma processes, and such material can eventually pinch off the openings so that voids result within the openings. Accordingly, oxide 34 is typically formed in a three-step process in an effort to avoid having the oxide prematurely pinch off the tops of the high-aspect-ratio trench openings.
The three-step process comprises a first step of high-density plasma deposition of oxide, a second step which is an etch to remove deposited materials from sidewalls of the trenches, and a third step which is to perform further high-density plasma deposition of oxide to completely fill the trenches. The high-density plasma depositions would be conducted at pressures below 10 mTorr, temperatures of from about 200° C. to about 500° C., a flow rate of silane of from about 10 standard cubic centimeters per minute (sccm) to about 500 sccm, and a flow rate of oxygen of from about 60 sccm to about 500 sccm. The etch occurring between the high-density plasma depositions will typically utilize NF3 at a flow rate of from about 100 sccm to about 1500 sccm, with a bias power to the substrate of from about 0 to 2000 watts, a temperature of from about 350° C. to about 750° C., a pressure below 10 mTorr, and a treatment time of from about 10 seconds to about 50 seconds.
Several problems can occur with the three-step process described above. For instance, the first high-density plasma deposition can form a significantly different amount of oxide along sidewalls of the relatively high-aspect-ratio trenches 18 and 20 relative to that formed along sidewalls of the relatively low-aspect-ratio trench 22 (with the terms “relatively high aspect ratio trench” and “relatively low aspect ratio trench” indicating that the referred-to trenches have high and low aspect ratios relative to one another, or in other words that the relatively high aspect ratio trench has a higher aspect ratio as compared to the relatively low aspect ratio trench). The effect of the etch on the oxide along the relatively low-aspect-ratio sidewalls of trench 22 can also be different than that along the relatively high-aspect-ratio sidewalls of trenches 18 and 20. Combined differences of etch rate and oxide thicknesses for the low-aspect-ratio trenches as compared to the high-aspect-ratio trench can lead to over-etching within the low-aspect-ratio trench 22, and under-etching with the high-aspect-ratio trenches 18 and 20. The over-etching can result in degradation of corners of materials 14, 16 and 12 proximate upper regions of the low-aspect-ratio trench, as illustrated by a degraded region 35 shown proximate trench 22. Also, the prior art processing may result in too much growth of oxide along the sidewalls of the high-aspect-ratio trenches 18 and 20 as compared to a rate at which the high-aspect-ratio trenches are filled, which can form the shown pinched crevices 37 (in other words, crevices with pinched-off upper regions) extending into the oxide within trenches 18 and 20.
Although only one degraded corner is shown within trench 22, it is to be understood that both upper corners of the shown cross-sectional view of the trench can be degraded. Also, although both of the high-aspect-ratio openings 18 and 20 are shown to have crevices extending therein, with both crevices being shown to extend to a similar depth, it is to be understood that the crevices would typically be non-uniform, with some of the high-ratio openings having relatively shallow crevices extending therein, and other openings having relatively deep crevices extending therein. Such non-uniformity creates complications in attempting to form consistent and uniform isolation regions across the entirety of a semiconductor substrate.
Referring next to FIG. 3, material 34 is subjected to planarization (such as, for example, chemical-mechanical polishing) to remove the material from over the surfaces of layer 16, and thus form the shown planarized surface 39. Crevices 37 extend through such planarized surface and into the oxide 34 of the relatively high-aspect-ratio trenches 18 and 20.
Referring next to FIG. 4, masking material 16 (FIG. 3) is removed with an etch selective for silicon nitride relative to silicon dioxide. The oxide 34 remaining within trenches 18, 20 and 22 forms trenched isolation regions. Unfortunately, crevices 37 can impair performance of the trenched isolation regions formed within trenches 18 and 20, and the degraded corner 35 can impair performance of the isolation region formed within trench 22. Accordingly, it is desired to develop new processing procedures which alleviate, and preferably prevent, formation of crevices 37 and degraded corner 35.